1. Field of the Invention
The present invention relates to a memory access delay control circuit for image motion compensation in a high definition television (hereinafter referred to as "HDTV"), and more particularly to a frame memory access delay control circuit which can adaptively delay access time of the memories for reading out and writing image signal data and simply control delay amount for image motion compensation.
2. Description of the Prior Art
Generally, image motion compensation is necessary to realize high picture quality in HDTV. For image motion compensation, two frame memories are used. One of the frame memories is for reading out image data to which a motion vector provided from an encoder is added, and the other frame memory is for writing an added result of the read data and inverse transformed image signal data, thereby performing image motion compensation. The image signal data read/write operation is alternately executed for every image frame and thus image motion compensation per frame can be performed. At this time, a time difference of as much as hundreds of clock pulses (about 140 to 150 clock pulses) should be generated between data read time and data write time and the delay time should be exactly controlled in order to maintain the time difference.
For the control of delay time as stated above, a conventional memory access delay control circuit uses a delay element or a memory for delay. That is, write address is stored in the memory for a required delay time and then is read out, operating the memory first-in first-out (hereinafter referred to as "FIFO"), thereby controlling the delay time.
As shown in FIG. 1, a conventional memory access delay control circuit comprises a counter 1 for increasing X and Y addresses per block by counting system clock pulses, starting from data with the value of 6-bit inputted macro block address (hereinafter referred to as "MBA") and 7-bit macro slice address (hereinafter referred to as "MSA") in the current processed block, a latch 2 for synchronizing X and Y address values by storing the counted value of counter 1, memory 3 for delaying an output signal of latch 2, being operated in FIFO, control section 4 for controlling the operation of memory 3, switching circuit 5 for switching the output signal of memory 3 per image frame, and two frame memories 6,7 for reading out and writing image data for one frame, of which the address signal is the output signal of switching circuit 5.
Operation of a conventional memory access delay control circuit will be described as follows.
First, counter 1 counts address values per block, starting from the inputted value of MBA and MSA and then outputs the increased X and Y addresses. Latch 2 stores X and Y addresses in order to synchronize the availability of addresses and then provides the synchronized availability of addresses to memory 3. Memory 3 enters the read-enable state or write-enable state under the control of control section 4 and stores the output signals of latch 2 during a specific delay time and then the outputs the signals. Each of output signals of memory 3 is respectively applied to each of frame memories 6,7 by switching circuit 5 as read address and write address, thereby performing image data read/write operation per frame.
However, there has been a problem in that the conventional circuit cannot utilize the existing basic circuits in HDTV but should include separate delay elements or memory for delay. In using memory for delay, high speed operation thereof as well as a separate control section for controlling the read/write operation thereof is always required, so that the manufacturing cost increases. And, when delay elements are used, more than one hundred delay elements for delaying hundreds of clock pulses are required, so that it is impossible to make the circuit practically. Moreover, whenever the delay amount varies, construction of the control section or the number of delay elements should be changed, causing operation of the circuit to be unstable.